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fm28v020 256-kbit (32 k 8) f-ram memory cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-86204 rev. *d revised march 11, 2014 2-mbit (128 k 16) f-ram memory features 256-kbit ferroelectric random access memory (f-ram) logically organized as 32 k 8 ? high-endurance 100 trillion (10 14 ) read/writes ? 151-year data retention (see the data retention and endurance table) ? nodelay? writes ? page mode operation ? advanced high-reliability ferroelectric process sram compatible ? industry-standard 32 k 8 sram pinout ? 70-ns access time, 140-ns cycle time superior to battery-backed sram modules ? no battery concerns ? monolithic reliability ? true surface mount solution, no rework steps ? superior for moisture, shock, and vibration ? resistant to negative voltage undershoots low power consumption ? active current 5 ma (typ) ? standby current 90 ? a (typ) low-voltage operation: v dd = 2.0 v to 3.6 v industrial temperature: ?40 ? c to +85 ? c packages: ? 28-pin small outline integrated circuit (soic) package ? 28-pin thin small outline package (tsop) type i ? 32-pin thin small outline package (tsop) type i restriction of hazardous substances (rohs) compliant functional overview the fm28v020 is a 32 k 8 n onvolatile memory that reads and writes similar to a standard sram. a ferroelectric random access memory or f-ram is nonvolatile, which means that data is retained after power is removed. it provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed sram (bbsram). fast write timing and high write endurance make the f-ram superior to other types of memory. the fm28v020 operation is similar to that of ot her ram devices and therefore, it can be used as a drop-in replacement for a standard sram in a system. re ad and write cycles may be triggered by ce or simply by changing the address. the f-ram memory is nonvolatile due to its unique ferroelectric memory process. these features make the fm28v020 ideal for nonvolatile memory applications requiring frequent or rapid writes. the device is available in a 28-pin soic, 28-pin tsop i and 32-pin tsop i surface mount pa ckages. device specifications are guaranteed over the industr ial temperature range ?40 c to +85 c. address latch ce control logic we row decoder a i/o latch & bus driver oe dq 32 k x 8 f-ram array . . . column decoder . . . 14-3 a 2-0 7-0 a 14-0 logic block diagram
fm28v020 document number: 001-86204 rev. *d page 2 of 21 contents pinouts .............................................................................. 3 pin definitions .................................................................. 4 device operation .............................................................. 5 memory operation....................................................... 5 read operation ........................................................... 5 write operation ........................................................... 5 page mode operation ................................................. 5 pre-charge operation.................................................. 5 sram drop-in replacement....................................... 6 endurance ................................................................... 6 maximum ratings............................................................. 7 operating range............................................................... 7 dc electrical characteristics .......................................... 7 data retention and endurance ....................................... 7 capacitance ...................................................................... 8 thermal resistance.......................................................... 8 ac test conditions .......................................................... 8 ac switching characteristics ......................................... 9 sram read cycle ...................................................... 9 sram write cycle..................................................... 10 power cycle timing ....................................................... 13 functional truth table................................................... 14 ordering information...................................................... 15 ordering code definitions ...... ................................... 15 package diagrams.......................................................... 16 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 21 worldwide sales and design supp ort............. .......... 21 products .................................................................... 21 psoc? solutions ...................................................... 21 cypress developer community................................. 21 technical support .................. ................................... 21
fm28v020 document number: 001-86204 rev. *d page 3 of 21 pinouts figure 1. 28-pin soic pinout figure 2. 28-pin tsop i pinout figure 3. 32-pin tsop i pinout dq 4 dq 5 dq 6 dq 7 oe a 8 a 13 we a 9 a 10 a 11 v dd ce dq 3 a 14 a 3 a 2 a 1 a 0 dq 0 dq 1 dq 2 v ss a 12 a 7 a 6 a 5 a 4 28-pin soic (x 8) top view (not to scale) 1 2 3 4 13 14 5 6 7 8 9 10 11 12 16 15 19 18 17 21 20 24 23 22 26 25 28 27 a 0 dq 0 dq 1 dq 2 dq 7 a 10 ce dq 6 dq 3 dq 5 a 1 we v dd a 14 a 12 a 7 a 6 a 5 a 4 oe a 11 a 9 a 8 a 13 28-pin tsop i (x 8) top view (not to scale) 22 23 24 5 6 25 26 27 28 1 2 3 4 10 9 13 12 11 15 14 18 17 16 20 19 21 7 8 a 3 a 2 v ss dq 4 a 0 dq 0 dq 1 dq 2 dq 7 a 10 ce dq 6 dq 3 dq 5 v dd a 1 nc we v dd a 14 a 12 a 7 a 6 a 5 a 4 oe a 11 a 9 a 8 a 13 32-pin tsop i (x 8) top view (not to scale) 1 2 3 4 13 14 5 6 7 8 9 10 11 12 20 19 23 22 21 25 24 28 27 26 30 29 32 31 15 16 18 17 a 3 nc a 2 nc v ss dq 4
fm28v020 document number: 001-86204 rev. *d page 4 of 21 pin definitions pin name i/o type description a 14 ?a 0 input address inputs : the 15 address lines select one of 32,768 bytes in the f-ram array. the lowest two address lines a 2 ?a 0 may be used for page mode read and write operations. dq 7 ?dq 0 input/output data i/o lines : 8-bit bidirectional data bus for accessing the f-ram array. we input write enable : a write cycle begins when we is asserted. the rising edge causes the fm28v020 to write the data on the dq bus to the f-ram array. the falling edge of we latches a new column address for page mode write cycles. ce input chip enable : the device is selected and a new memory access begins on the falling edge of ce . the entire address is latched internally at this point. subsequent changes to the a 2 ?a 0 address inputs allow page mode operation. oe input output enable : when oe is low, the fm28v020 drives the da ta bus when the valid read data is available. deasserting oe high tristates the dq pins. v ss ground ground for the device. must be connected to the ground of the system. v dd power supply power supply input to the device. nc no connect no connect. this pin is not connected to the die.
fm28v020 document number: 001-86204 rev. *d page 5 of 21 device operation the fm28v020 is a bytewide f-ram memory logically organized as 32,768 8 and accessed using an industry-standard parallel interface. all data written to the part is immediately nonvolatile with no delay. the device offers page mode operation, which provides high-speed access to addresses within a page (row). access to a different page requires that either ce transitions low or the upper address (a 14 ?a 3 ) changes. see the functional truth table on page 14 for a complete description of read and write modes. memory operation users access 32,768 memory locations, each with 8 data bits through a parallel interface. the f-ram array is organized as eight blocks, each having 512 ro ws. each row has eight column locations, which allow fast access in page mode operation. when an initial address is latched by the falling edge of ce , subsequent column locations may be accessed without the need to toggle ce . when ce is deasserted high, a pre-charge operation begins. writes occur immediately at the end of the access with no delay. the we pin must be toggled for each write operation. the write data is stored in the nonvolatile memory array immediately, which is a feature unique to f-ram called nodelay writes. read operation a read operation begins on the falling edge of ce . the falling edge of ce causes the address to be latched and starts a memory read cycle if we is high. data becomes available on the bus after the access time is met. when the address is latched and the access completed, a new access to a random location (different row) may begin while ce is still low. the minimum cycle time for random addresses is t rc . note that unlike srams, the fm28v020's ce -initiated access time is faster than the address access time. the fm28v020 will drive the data bus when oe is asserted low and the memory access time is met. if oe is asserted after the memory access time is met, the data bus will be driven with valid data. if oe is asserted before completing the memory access, the data bus will not be driven un til valid data is available. this feature minimizes supply current in the system by eliminating transients caused by invalid data being driven to the bus. when oe is deasserted high, the data bus will remain in a hi-z state. write operation in the fm28v020, writes occur in the same interval as reads. the fm28v020 supports both ce and we controlled write cycles. in both cases, the address is latched on the falling edge of ce . in a ce -controlled write, the we signal is asserted before beginning the memory cycle. that is, we is low when the device is activated with the chip enable. in this case, the device begins the memory cycle as a wr ite. the fm28v020 will not drive the data bus regardless of the state of oe as long as we is low. input data must be valid when ce is deasserted high. in a we -controlled write, t he memory cycle begins on the fa lling edge of ce . the we signal falls some time later. therefore, the memory cycle begins as a read. the data bus will be driven if oe is low; however, it will be hi-z when we is asserted low. the ce and we controlled write timing cases are shown on the page 12 . in the figure 10 on page 12 diagram, the data bus is shown as a hi-z condition while the chip is write-enabled and before the required setup time. although this is drawn to look like a mid-level voltage, it is recommended that all dq pins comply with the minimum v ih /v il operating levels. write access to the array begins on the falling edge of we after the memory cycle is initiated. th e write access terminates on the rising edge of we or ce , whichever comes first. a valid write operation requires the user to m eet the access time specification before deasserting we or ce . the data setup time indicates the interval during which data cannot change before the end of the write access (rising edge of we or ce ). unlike other nonvolatile memory technologies, there is no write delay with f-ram. because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. page mode operation the fm28v020 provides the user fast access to any data within a row element. each row has eight column-address locations. address inputs a 2 ?a 0 define the column address to be accessed. an access can start anywhere within a row and other column locations may be accessed without the need to toggle the ce pin. for fast access reads, after the first data byte is driven to the bus, the column address inputs a 2 ?a 0 may be changed to a new value. a new data byte is then driven to the dq pins. for fast access writes, the first write pulse defines the first write access. while ce is low, a subsequent write pulse along with a new column address provides a page mode write access. pre-charge operation the pre-charge operation is an in ternal condition in which the memory state is prepared for a new access. pre-charge is user-initiated by driving the ce signal high. it must remain high for at least the minimum pre-charge time, t pc . pre-charge is also activated by changing the upper addresses, a 14 ?a 3 . the current row is first closed before accessing the new row. the device automatically detects an upper order address change, which starts a pre-charge operation. the new address is latched and the new read data is valid within the t aa address access time; see figure 6 on page 11 . a similar sequence occurs for write cycles; see figure 11 on page 12 . the rate at which random addresses can be issued is t rc and t wc , respectively.
fm28v020 document number: 001-86204 rev. *d page 6 of 21 sram drop-in replacement the fm28v020 is designed to be a drop-in replacement for standard asynchronous srams. the device does not require ce to toggle for ea ch new address. ce may remain low indefinitely while v dd is applied. while ce is low, the device automatically detects address changes and a new access begins. it also allows page mode operation at speeds up to 15 mhz. a typical application is shown in figure 4 . it shows a pull-up resistor on ce , which will keep the pin high during power cycles, assuming the mcu / mpu pi n tristates during the reset condition.the pull-up resistor value should be chosen to ensure the ce pin tracks v dd to a high enough value, so that the current drawn when ce is low is not an issue. a 10-k ? resistor draws 330 a when ce is low and v dd = 3.3 v. note that if ce is tied to ground, the user must be sure we is not low at power-up or power-down events. if ce and we are both low during power cycles, da ta will be corrupted. figure 5 shows a pull-up resistor on we , which will keep the pin high during power cycles, assuming the mcu/ mpu pin tristates during the reset condition.the pull-up resi stor value should be chosen to ensure the we pin tracks v dd to a high enough value, so that the current drawn when we is low is not an issue. a 10-k ? resistor draws 330 a when we is low and v dd = 3.3 v. for applications that require the lowest power consumption, the ce signal should be active only during memory accesses. due to the external pull-up resistor, some supply current will be drawn while ce is low. when ce is high, the device draws no more than the maximum standby current i sb . ce toggling low on every address access is perfectly acceptable in fm28v020. endurance the fm28v020 is capable of being accessed at least 10 14 times ? reads or writes. an f-ram me mory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis. the f-ram architecture is based on an array of rows and columns. rows are defined by a 14-3 and column addresses by a 2 -a 0 . the array is organized as 4k rows of eight bytes each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation if the addressing is contiguous in nature. the user may choose to write cpu instructions and run them from a certain address space. table 1 shows endurance calculations for a 256-byte repeating loop, which includes a starting address, seven-pa ge mode accesses, and a ce pre-charge. the numbe r of bus clock cycles needed to complete a eight-byte read transaction is 1 + 7 + 1 or 9 clocks. the entire loop causes each byte to experience only one endurance cycle. the f-ram read and write endur ance is virtually unlimited. figure 4. use of pull-up resistor on ce figure 5. use of pull-up resistor on we mcu / mpu ce we oe a 14-0 dq 7-0 fm28v020 v dd mcu / mpu ce we oe a 14-0 dq 7-0 fm28v020 v dd table 1. time to reach 100 trillion cycles for repeating 256-byte loop bus freq (mhz) bus cycle time (ns) 256-byte transaction time ( ? s) endurance cycles/sec endurance cycles/year years to reach 10 14 cycles 10 100 28.8 34,720 1.09 x 10 12 91.7 5 200 57.6 17,360 5.47 x 10 11 182.8
fm28v020 document number: 001-86204 rev. *d page 7 of 21 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +125 ? c maximum junction temperature ................................... 95 ? c supply voltage on v dd relative to v ss ........?1.0 v to + 4.5 v voltage applied to outputs in high z state .................................... ?0.5 v to v dd + 0.5 v input voltage .......... ?1.0 v to + 4.5 v and v in < v dd + 1.0 v transient voltage (< 20 ns) on any pin to ground potential ............ ..... ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount pb soldering temperature (3 seconds) ........ .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration) .... 15 ma static discharge voltage human body model (aec-q100- 002 rev. e) ............ 2 kv charged device model (aec-q100-011 rev. b) .. 1.25 kv machine model (aec-q100-003 rev. e) ................. 200 v latch-up current ................................................... > 140 ma operating range range ambient temperature (t a ) v dd industrial ?40 ? c to +85 ? c 2.0 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [1] max unit v dd power supply voltage 2.0 3.3 3.6 v i dd v dd supply current v dd = 3.6 v, ce cycling at min. cycle time. all inputs toggling at cmos levels (0.2 v or v dd ? 0.2 v), all dq pins unloaded. ?58ma i sb standby current v dd = 3.6 v, ce at v dd , all other pins are static and at cmos levels (0.2 v or v dd ? 0.2 v) ? 90 150 a i li input leakage current v in between v dd and v ss ??+ 1a i lo output leakage current v out between v dd and v ss ??+ 1a v ih input high voltage 0.7 v dd ?v dd + 0.3 v v il input low voltage ? 0.3 ? 0.3 v dd v v oh1 output high voltage i oh = ?1.0 ma, v dd > 2.7 v 2.4 ? ? v v oh2 output high voltage i oh = ?100 a v dd ? 0.2 ? ? v v ol1 output low voltage i ol = 1 ma, v dd > 2.7 v ? ? 0.4 v v ol2 output low voltage i ol = 150 a ? ? 0.2 v data retention and endurance parameter description test condition min max unit t dr data retention at +85 ? c 10 ? years at +75 ? c38? at +65 ? c151? nv c endurance over operating temperature 10 14 ? cycles note 1. typical values are at 25 c, v dd = v dd (typ). not 100% tested.
fm28v020 document number: 001-86204 rev. *d page 8 of 21 ac test conditions input pulse levels ...................................................0 v to 3 v input rise and fall times (10%?90%) ........................... < 3 ns input and output timing reference levels ....................... 1.5 v output load capacitance ............................................... 30 pf capacitance parameter description test conditions max unit c i/o input/output capacitance (dq) t a = 25 ? c, f = 1 mhz, v dd = v dd (typ) 8 pf c in input capacitance 6pf thermal resistance parameter description test conditions 28-pin soic 28-pin tsop i 32-pin tsop i unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 59 108 84 ? c/w ? jc thermal resistance (junction to case) 30 29 26 ? c/w
fm28v020 document number: 001-86204 rev. *d page 9 of 21 ac switching characteristics over the operating range parameters [2] description min max unit cypress parameter alt parameter sram read cycle t ce t ace chip enable access time ? 70 ns t rc ? read cycle time 140 ? ns t aa ? address access time ? 140 ns t oh t oha output hold time 20 ? ns t aap ? page mode address access time ? 40 ns t ohp ? page mode output hold time 3 ? ns t ca ? chip enable active time 70 ? ns t pc ? pre-charge time 70 ? ns t as t sa address setup time (to ce low) 0? ns t ah t ha address hold time (ce controlled) 70 ? ns t oe [3] t doe output enable access time ? 20 ns t hz [4, 5] t hzce chip enable to output hi-z ? 10 ns t ohz [4, 5] t hzoe output enable high to output hi-z ? 10 ns notes 2. test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 0 to 3 v, output loading of the specified i ol /i oh and load capacitance shown in ac test conditions on page 8 . 3. for v dd < 2.7 v, t oe max is 25 ns. 4. t hz and t ohz are specified with a load capacitance of 5 pf. transition is measured when the outputs enter a high impedance state. 5. this parameter is characterized but not 100% tested.
fm28v020 document number: 001-86204 rev. *d page 10 of 21 sram write cycle t wc t wc write cycle time 140 ? ns t ca ? chip enable active time 70 ? ns t cw t sce chip enable to write enable high 70 ? ns t pc ? pre-charge time 70 ? ns t pwc ? page mode write enable cycle time 35 ? ns t wp t pwe write enable pulse width 18 ? ns t as t sa address setup time (to ce low) 0 ? ns t ah t ha address hold time (ce controlled) 70 ? ns t asp ? page mode address setup time (to we low) 5 ? ns t ahp ? page mode address hold time (to we low) 20 ? ns t wlc t pwe write enable low to chip disabled 25 ? ns t wla ? write enable low to a 14-3 change 25 ? ns t awh ? a 14-3 change to write enable high 140 ? ns t ds t sd data input setup time 15 ? ns t dh t hd data input hold time 0 ? ns t wz [6, 7] t hzwe write enable low to output hi-z ? 10 ns t wx [7] ? write enable high to output driven 5 ? ns t ws [7, 8] ? write enable to ce low setup time 0 ? ns t wh [7, 8] ? write enable to ce high hold time 0 ? ns ac switching characteristics (continued) over the operating range parameters [2] description min max unit cypress parameter alt parameter notes 6. t wz is specified with a load c apacitance of 5 pf. trans ition is measured when the ou tputs enter a high impedance state. 7. this parameter is characterized but not 100% tested. 8. the relationship between ce and we determines if a ce or we controlled write occurs.
fm28v020 document number: 001-86204 rev. *d page 11 of 21 figure 6. read cycle timing 1 (ce low, oe low) figure 7. read cycle timing 2 (ce controlled) figure 8. page mode read cycle timing [9] valid data a dq t rc previous data t oh t aa t oh 14-0 7-0 t oh d out a oe dq t as t ce t ca t pc t oe t ohz t hz t ah ce 14-0 7-0 a oe dq t as t ca a t oe t ce t ohz t aap t ohp t hz t pc col 0 data 0 col 1 data 1 col 2 data 2 ce 14-3 2-0 7-0 note 9. although sequential column addressing is shown, it is not required
fm28v020 document number: 001-86204 rev. *d page 12 of 21 figure 9. write cycle timing 1 (we controlled) [10] figure 10. write cycle timing 2 (ce controlled) figure 11. write cycle timing 3 (ce low) [10] t hz t dh d in ce a we t ca t pc dq t wp t cw t as d out d out t ds t wx t wz t wlc 14-0 7-0 we dq t ca t pc t ws t as t wh t dh t ds ce t ah d in a t ca t pc t ws t as t wh t dh t ds t ah 14-0 7-0 t dh t wz t wx d in a we dq t wc t wla t ds t awh d out d out d in 14-0 7-0 note 10. oe (not shown) is low only to show the effect of we on dq pins.
fm28v020 document number: 001-86204 rev. *d page 13 of 21 figure 12. page mode write cycle timing t asp t dh a we t ca t pc dq t cw a col 0 col 1 data 0 col 2 t as t ds data 1 t wp data 2 oe t ahp t pwc t ah ce t wlc 14-3 2-0 7-0 power cycle timing over the operating range parameter description min max unit t pu power-up (after v dd min. is reached) to first access time 250 ? s t pd last write (we high) to power down time 0 ? s t vr [11] v dd power-up ramp rate 50 ? s/v t vf [11] v dd power-down ramp rate 100 ? s/v figure 13. power cycle timing v dd t vf 1.0 v v dd min min v dd 1.0 v t vr t pu t pd access allowed note 11. slope measured at any point on the v dd waveform.
fm28v020 document number: 001-86204 rev. *d page 14 of 21 functional truth table ce we a 14 -a 3 a 2 -a 0 operation [12, 13] h x x x standby/idle l h h v v v v read l h no change change page mode read l h change v random read l l l v v v v ce -controlled write [13] l vvwe -controlled write [13, 14] l no change v page mode write [15] l x x x x x x starts pre-charge notes 12. h = logic high, l = logic low, v = valid data, x = don't care, = toggle low, = toggle high. 13. for write cycles, data-in is latched on the rising edge of ce or we , whichever comes first. 14. we -controlled write cycle begins as a read cycle and then a 14 -a 3 is latched. 15. addresses a 2 -a 0 must remain stable for at least 15 ns during page mode operation.
fm28v020 document number: 001-86204 rev. *d page 15 of 21 ordering code definitions ordering information access time (ns) ordering code package diagram package type operating range 70 fm28v020-sg 51-85026 28-pin soic industrial FM28V020-SGTR 51-85026 28-pin soic fm28v020-t28g 001-91155 28-pin tsop i fm28v020-t28gtr 001-91155 28-pin tsop i fm28v020-tg 001-91156 32-pin tsop i fm28v020-tgtr 001-91156 32-pin tsop i all the above parts are pb-free. option: blank = standard; tr = tape and reel package type: sg = 28-pin soic; t28g = 28-pin tsop i; tg = 32-pin tsop i density: 020 = 256-kbit voltage: v = 2.0 v to 3.6 v parallel f-ram cypress 28 fm v 020 - sg tr
fm28v020 document number: 001-86204 rev. *d page 16 of 21 package diagrams figure 14. 28-pin soic package outline, 51-85026 51-85026 *g
fm28v020 document number: 001-86204 rev. *d page 17 of 21 figure 15. 28-pin tsop i package outline, 001-91155 package diagrams (continued) 001-91155 **
fm28v020 document number: 001-86204 rev. *d page 18 of 21 figure 16. 32-pin tsop i package outline, 001-91156 package diagrams (continued) 001-91156 **
fm28v020 document number: 001-86204 rev. *d page 19 of 21 acronyms document conventions units of measure acronym description cpu central processing unit cmos complementary metal oxide semiconductor jedec joint electron devices engineering council jesd jedec standards eia electronic industries alliance f-ram ferroelectric random access memory i/o input/output mcu microcontroller unit mpu microprocessor unit rohs restriction of hazardous substances rw read and write sram static random access memory tsop thin small outline package symbol unit of measure c degree celsius hz hertz khz kilohertz k ? kilohm mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond m ? megaohm ns nanosecond ? ohm % percent pf picofarad v volt w watt
fm28v020 document number: 001-86204 rev. *d page 20 of 21 document history page document title: fm28v020, 256- kbit (32 k 8) f-ram memory document number: 001-86204 rev. ecn no. orig. of change submission date description of change ** 3912932 gvch 02/25/2013 new data sheet. *a 3924836 gvch 03/07/2013 chan ged to production status added 28-pin tsop package type changed i dd limit min spec from 7 ma to 5 ma and max spec from 12 ma to 8 ma. read cycle ac parameters: changed t aap spec value from 60 ns to 40 ns and t oe spec value from 15 ns to 20 ns write cycle ac parameters: changed t pwc spec value from 30 ns to 35 ns and t ahp spec value from 15 ns to 20 ns *b 4000965 gvch 05/15/2013 added appendix a - errata for fm28v020 *c 4045491 gvch 06/30/2013 all errata items are fixed and the errata is removed. *d 4274812 gvch 03/11/2014 converted to cypress standard format updated maximum ratings table - removed moisture sensitivity level (msl) - added junction temperature and latch up current updated data retention and endurance table added thermal resistance table removed package marking scheme (top mark)
document number: 001-86204 rev. *d revised march 11, 2014 page 21 of 21 all products and company names mentioned in this document may be the trademarks of their respective holders. fm28v020 ? cypress semiconductor corporation, 2013-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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